1. Field of the Invention
The present invention relates in general to data communication transceivers and in particular to an interpolated timing recovery system for synchronizing communications between two transceivers.
2. Description of Related Art
The IEEE 802.3ab (“Ethernet”) standard defines a digital media interface commonly used for transmitting data between computers linked through a network. The standard includes a “1000BASE-T” protocol enabling transceivers to communicate with one another through pulse amplitude modulation (PAM) signals conveyed on a set of four category 5 (CAT5) unshielded twisted-pair (UTP) conductors. A transceiver operating in accordance with the 1000BASE-T protocol can concurrently transmit and receive one 8-bit word every 8 nsec, thereby providing an effective communication rate of one Gigabit per second in both directions.
FIG. 1 illustrates a prior art 1000BASE-T transceiver 10 in block diagram form. Transceiver 10 includes a transmit physical coding sublayer (PCS) 12 for scrambling and encoding an incoming sequence of 8-bit words Tx to produce four sequences of 3-bit data words Tx,a-Tx,d, each of which is an integer value of the set {−2, −1, 0, +1 or +2}. Each data word Tx,a-Tx,d is supplied as input to a separate one of a set of four “physical medium attachment” (PMA) units 16(A)–16(D), and each PMA unit 16(A)–16(D) generates an output 1000BASE-T signal on a corresponding one of four UTPs A–D in response to its input data sequence Tx,a-Tx,d. Each PMA unit 16(A)–16(D) also detects a data sequence conveyed by an incoming 1000BASE-T signal transmitted by a remote transceiver on its corresponding UTP A-D and supplies that data sequence Rx,a-Rx,d to receive PCS 14. Receive PCS 14 de-scrambles and decodes the four Rx,a-Rx,d data sequences from PMAs 16(A)–16(D) to produce a single 8-bit output data word sequence Rx matching the remote transceiver's 8-bit input data sequence.
PCS 12, PCS 14, PMAs 16 and the remote transceiver all operate synchronously at the 125 MHz rate with which data is forwarded on UTPs A–D. When an input M/S signal tells transceiver 10 to act as a “master”, a timing recovery system 15 supplies a free running 125 MHz clock signal CLK1 to transmit PCS 12, receive PCS 14 and PMAs 16 for controlling the timing of their operations. The remote transceiver, acting as a slave, synchronizes its own internal 125 MHz clock to CLK1 based on the timing with which data arrives from transceiver 10. Conversely, when the M/S signal tells local transceiver 10 to act as the slave, timing recovery system 15 adjusts the frequency and phase of its output clock signal CLK1 based on the timing of data streams D3, D4 PMA 16(A) derives from the signal arriving on UTP A from the remote transceiver.
FIG. 2 illustrates prior art PMA 16(A) and timing recovery system 15 of FIG. 1 in more detailed block diagram form; PMAs 16(B)–16(D) of FIG. 1 are similar. PMA 16(A) includes a transmitter 18 for sending an analog signal A1 outward on UTP A in response to the incoming 3-bit Tx,a data sequence, a receiver 20 for generating the 3-bit output data sequence Rx,a in response to an incoming 1000BASE-T signal A2 arriving on UTP A, and a “hybrid” circuit 22 for coupling the transmitter and receiver to UTP A.
Transmitter 18 includes a trellis code modulation (TCM) encoder 24 for converting the incoming Tx,a data sequence into a 125 MHz data sequence T1x,a indicating the voltage of each successive level of the outgoing analog signal A1. A digital-to-analog converter (DAC) 26 converts each word of the partial response sequence output T1x,a to a voltage, a low pass filter (LPF) 27 smoothes the DAC output signal, and a driver 28 amplifies the output of LPF 27 to produce the analog signal A1 transmitted outward on UTP A via hybrid 22 to the remote transceiver.
Hybrid 22 passes an incoming analog signal arriving on UTP A from the remote transceiver as an analog signal A2 input to receiver 20. Receiver 20 includes an amplifier 32 for amplifying the A1 signal with an adjustable gain and offset. A low pass filter 34 removes high frequency noise from the amplifier output signal to produce an analog signal A3. An analog-to-digital converter (ADC) 36 digitizes the A3 signal to produce a sequence of data elements D1 representing successively sampled magnitudes of the A3 signal. Automatic gain control (AGC) and baseline wander (BLW) control circuits 33 control the gain and offset of amplifier 32 to keep the peak-to-peak amplitude of the analog signal A3 near the full input range of ADC 36.
A clock signal CLK4 synchronized to the remote transmitter's CLK1 signal clocks ADC 36. The CLK4 signal shifts each element of the D1 sequence into a first-out (FIFO) buffer 37 and the local CLK1 clock signal shifts the D1 sequence out of FIFO buffer 37.
The amount of echo distortion of the incoming A2 signal is proportional to the magnitude of the A1 signal transmitter 18 is currently sending outward on UTP A. The amount of near end crosstalk (NEXT) distortion in the incoming A2 signal is proportional to the magnitude of the outgoing A1 signals currently being transmitted outward by transmitters within the other three PMAs 16(B)–16(D) of FIG. 1. An echo/NEXT canceller circuit 38 monitors the T1x,a -T1x,d data sequences produced by all four transmitters and supplies an offset data sequence D2 to a summer 40 representing the magnitude of echo and NEXT distortion in the incoming signal.
A summer 40 subtracts the D2 sequence generated by echo/NEXT canceller 38 from data sequence D1 output of FIFO buffer 37 to produce a data sequence D3 that is compensated for echo and NEXT distortion. An adaptive feed forward equalizer (FFE) 42 compensates the D3 sequence for channel response (distortions introduced by the incoming signal path) to produce a sequence D4. A trellis code modulation decoder 44 decodes the D4 sequence to produce an Rx,a sequence supplied to PCS 14 of FIG. 1 replicating the Tx,a input sequence of the remote transceiver's A channel PMA.
The 125 MHz clock signal CLK1 output of timing recovery system 15 clocks all of the digital components of transmitter 18 and receiver 20 that operate at 125 MHz. Timing recovery system 15 includes a clock signal generator 46 for producing a free-running 125 MHz clock signal CLK5 and a variable frequency oscillator (VFO) 58 for producing a 125 MHz clock signal CLK4 that is frequency locked to the remote transceiver's CLK1 signal. A multiplexer 48 controlled by the M/S signal selects the CLK5 signal as the source of clock signal CLK1 when the transceiver operate as master and selects the CLK4 signal as the source of clock signal CLK1 when the transceiver operates as slave.
VFO 58 produces clock signal CLK4 at a frequency controlled by input data D9 produced by devices 50–52 in response to the “soft decision” data D4 sequence output of FFE 42 which represents the data conveyed by the incoming A2 signal. When transceiver 10 is operating in the slave mode, elements of the data sequence D4 appear at the remote transceiver's 125 MHz clock rate. A slicer 50 “rounds off” each 8-bit data sequence element D4 output of FFE 42 of receiver 20 to produce a corresponding 3-bit “hard decision” data sequence element D5 representing the nearest integer value which acts as an estimate of the integer value of the D4 data. When the phase and frequency of clock signal CLK4 are correctly adjusted, the current D4 sequence element will be a whole number and will match D5. When the phase of clock signal CLK4 signal is incorrect, the current D4 sequence element will have a fractional component and will be larger or smaller than is corresponding D5 sequence element. Characteristic patterns in differences in between corresponding D4 and DS elements are indicative of phase errors in clock signal CLK4 relative to 125 MHz clock rate of the D4 data. A phase error detector (PED) 51 processes the D4 and D5 sequences to generate data D6 representing the phase error and a filter 52 smoothes the D6 sequence to produce a data sequence D7. The D7 data output of filter 52, which represents the error in the phase of clock signal CLK4, acts as input to VFO 58 and finely adjusts the phase and frequency of clock signal CLK4 to frequency lock it to the remote transceiver's CLK1 signal.
The CLK4 signal is somewhat jittery since VFO 58 is controlled by a feedback loop. Jitter in clock signal CLK4 introduces distortion the D1 sequence output of ADC 36 and such distortion affects the performance of the FFE 42 since a conventional FFE's ability adapt to the predictable channel response distortion is degraded when confronted with unpredictable distortion resulting from random variations in phase of the transceiver's sampling clock. The degradation in FFE performance increases the probability of data transmission errors. Also, when the transceiver is acting in the slave mode, the CLK1 signal supplied to DAC 26 is somewhat jittery because it is derived from the jittery CLK4 signal. Such jitter in the CLK1 input to DAC 28 causes unpredictable distortion in the analog signal A1 sent to the remote transceiver and further adds to the difficulty for the remote transceiver's FFE has in adapting to the channel response.
What is needed is a transceiver architecture allowing two transceivers to communicate with one another even though they concurrently employ free-running clock signals to control the rate at which they encode data into the analog output signals they transmit and to control the rate at which they digitize the analog signals they receive.